Next Big Future  September 10, 2023
The semiconductor industry is expected to evolve from 2D to 3D DRAM over the next five to eight years based on current technical capabilities. Lam is simulating DRAM’s untested future by creating proposals for what 3D DRAM architecture could look like. Some suggestions for a 3D DRAM to address include – Scaling issues, Stacking challenges, Shrinking footprints, Innovative connections, Via arrays, Process requirements. Driving higher density of bits by reducing the footprint of the capacitors by making them taller will not be possible because etch and deposition processes for capacitor fabrication cannot handle the extreme (high) aspect ratio. Lam’s designers have proposed several changes to provide more space for capacitor processing while reducing the silicon area, thereby shrinking the nanosheets’ footprint. A DRAM structure is composed of a conductive material/structure which provides the carriers (current) to be injected into a transistor. They introduced gate-all-around transistors to further reduce the silicon active area, made the capacitors short and wide, increased the quantity of transistors/capacitors per bitline contact reconfiguring nanosheet. The first iteration of a stacked 3D DRAM would be 28 layers tall… read more.