Intel’s Stacked Nanosheet Transistors Could Be the Next Step in Moore’s Law

IEEE Spectrum  December 29, 2020
The logic circuits behind just about every digital device today rely on a pairing of NMOS and PMOS. Researchers at Intel showed a different way: stacking the pairs so that one is atop the other. The scheme effectively cut the footprint of a simple CMOS circuit in half, meaning a potential doubling of transistor density on future ICs. The main part of the transistor consisting of a vertical fin of silicon as it does today, the nanosheet’s channel region consists of multiple, horizontal, nanometers-thin sheets stacked atop one another. They built an inverter using these devices. Building stacked nanosheets is a self-aligned process because it builds both devices in essentially the same step avoiding misalignments during bonding wafers…read more.

NMOS and PMOS devices usually sit side-by-side on chips. Intel has found a way to build them atop one another, compressing circuit sizes. Credit: Intel

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